Article: Distance-Based ISA for Efficient Register Management
Despite the fact that modern processors’ insane capabilities of parallel instruction executions and scheduling capabilities, they still face the problem of register renaming process, a process that follows right after decoding process.
Register Renaming is a technique used in modern CPUs (1995 and later) to avoid false data dependencies during instruction execution, especially in out-of-order execution. Consider the following scenario:
R1 = R2 + R3 ; Instruction A R2 = R4 + R5 ; Instruction B
Here, instruction B writes R4 + R5 into R2, which is read in instruction A. When
executing several instructions at once, such as parallel and superscalar execution,
WAR (Write After Read) hazard might happen to R2, meaning that the
value of R2 can be written in instruction B before it is read in instruction
A.
By reserving more physical registers than logical ones, R2 in instruction B can be
stored somewhere else to avoid WAR. For example:
P1 = P2 + P3 ; Instruction A: R1 → P1, R2 → P2, R3 → P3 P9 = P4 + P5 ; Instruction B: R2 → P9
In summary, the main use of register renaming is for out-of-order execution to maximize throughput. Remind that out-of-order instructions is different from re-ordered instructions for pipelining, since the latter does not require additional physical registers.
Register renaming demands heavily multi-ported memory, which consumes substantial chip area and power, making it difficult to scale the rename width (number of instructions that can be renamed per cycle) easily. Additionally, maintaining the mapping between logical and physical registers is inherently complex. For instance, in an event of a branch misprediction, all renaming tied to the mispredicted instructions must be reverted, requiring the mapping table to be restored to its prior state. As the Re-order buffer (ROB) grows, these overheads increase proportionally.
Instead of reusing registers, distance-based instruction set architecture (ISA) uses a sliding buffer to store the results of instructions. The result of each instruction is stored in the sliding buffer (reserved physical registers) so that register renaming is unnecessary. Consider the following example:
X = [2] + [3]
where [2] means “use the result of the instruction that is 2 instructions before me”.
The indecies are managed by a register pointer (RP), indicating the offset between
“current instruction” and “previous instructions”. Since there is a limited number
of physical registers. RP resets its value every time it reaches the buffer’s
capacity.
This approach indeed eliminates the need for register-renaming hardware, thereby resolving the bottlenecks associated with traditional register-based architectures.
Also, as shown in the article, there are other methods that implements this novel ISA, such as Clockhands and TURBULENCE. Nevertheless, these methods all relate to the author of STRAIGHT: Hidetsugu IRIE from The University of Tokyo.