Recently I embarrassed myself by discovering that DRAMs do not use flip-flops, which I thought they do for a very long time. In fact, they use a transistor and a capacitor (depends on implementation; In this configuration it is also called 1T1C) for each cell. The transistor decides if there should be currents flowing through the circuit and the capacitor stores a bit by getting charged or loses one by releasing charge.
When storing a 1, the word line turns on and applies enough voltage so that the transistor (usually NMOS) can flow currents, allowing non-negative voltage from the bit line to store charges in the capacitor. When releasing a 1 (getting a 0), the word line is turned on like before, but this time the bit line is 0 V so that the charges flow back the bit line. However, the charges that are stored in the capacitor does not just stay there, they leak. So, the controller on DRAM needs to read the cells’ values periodically and writes them again to ensure the values are not lost. Although the cost of reading & writing can be ignored because that does not affect main processor, current leakage is a big issue.
I don’t know how to fix this problem, but I have heard that Artificial Intelligence of Things (AIoT) use SRAM instead of DRAM for minimum power usage (somewhere like sub or single digit milliW). SRAM only uses flip-flops to store data, so it simply consumes constant power to function.